Complete test generation method for all stuck-at faults in combinational circuits

Guran H., HALICI U.

International Journal of Electronics, cilt.68, sa.5, ss.657-666, 1990 (SCI-Expanded) identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 68 Sayı: 5
  • Basım Tarihi: 1990
  • Doi Numarası: 10.1080/00207219008921209
  • Dergi Adı: International Journal of Electronics
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.657-666
  • Ankara Üniversitesi Adresli: Hayır

Özet

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure. © 1990 Taylor and Francis Ltd.