Complete test generation method for all stuck-at faults in combinational circuits

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Guran H., HALICI U.

International Journal of Electronics, vol.68, no.5, pp.657-666, 1990 (SCI-Expanded, Scopus)

• Publication Type: Article / Article
• Volume: 68 Issue: 5
• Publication Date: 1990
• Doi Number: 10.1080/00207219008921209
• Journal Name: International Journal of Electronics
• Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
• Page Numbers: pp.657-666
• Ankara University Affiliated: No

Abstract

In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure. © 1990 Taylor and Francis Ltd.